Samsung has already delivered the first batch of HBM4 memory to its customers and announced that it has begun mass production of the new standard.
The HBM4 chips are built on the 6th generation of the 10nm-class DRAM process, called “1c”. Note that DRAM is not like CPU cores, so nodes are not comparable. HBM4 products also use a 4nm logic base die for higher performance.
To put some numbers on it, HBM4 can deliver speeds of up to 11.7Gbps – per pin! This is 46% higher than the industry standard, which is set at 8Gbps. Since there are 2,048 pins, the total bandwidth is 3.3 terabytes per second. This is a 2.7-fold increase compared to HBM3E.
Note that when it standardized HBM4, JEDEC (the governing body for computer RAM) decided to reduce the per-pin bandwidth compared to HBM3E (9.6Gbps), while doubling the number of pins from 1,024 to 2,048. This was done for better power efficiency and better thermal management.
Therefore, Samsung has already topped the target per-pin speed for HBM4 and has surpassed HBM3E speeds. But he thinks he can do even better – he says in the future he could produce chips with 13 Gbps capacity per pin.
Currently, Samsung’s HBM4 memory uses 12-layer stacking technology and is available in capacities ranging from 24GB to 36GB. The company will adapt to the needs of its customers and can offer 16-layer designs with up to 48GB capacity.
The Samsung-designed HBM4 memory uses low voltage through silicon vias and a power distribution network, improving power efficiency by 40%. Additionally, the memory stack has 10% lower heat resistance and 30% better heat dissipation than the HBM3E.
Samsung expects to see strong demand for its memory products this year – it estimates sales will triple compared to 2025. In anticipation of this, the company is working to expand HBM4 production capacity.
As for what’s next, samples of the next generation HBM4E memory will be delivered to customers in the second half of 2026. Next year, it will send custom HBM samples to customers (designed according to their specifications).
Song Joon Hwang, Executive Vice President and Head of Memory Development, Samsung Electronics, said, “Instead of taking the traditional path of using existing proven designs, Samsung took the leap and adopted the most advanced nodes such as 1C DRAM and 4nm logic process for HBM4. By leveraging our process competitiveness and design optimization, we are able to secure sufficient performance headroom, enabling us to meet our customers’ growing demands for higher performance. are there when they need them.”
